(A) Field of the Invention
The present invention relates to a programmable logic device (hereinafter referred to as "PLD") including a plurality of programmable logic elements (hereinafter referred to "PLE") having a plurality of flip-flop circuits.
(B) Prior Art
There has heretofore been known a PLD in which optional logic circuits are arranged by a user who programs the circuits. For example, there is the one disclosed in Japanese Patent Unexamined Publication Nos. 198919/1986 and 224520/1986.
FIG. 5 is a block diagram of a PLD. In this PLD, a plurality of PLEs 101 are provided on a chip 100, and further, input terminals and output terminals of PLEs 101 can be desirably connected to each other by programmable wiring means 102 in vertical and horizontal directions between the terminals.
The PLE 101 has a combinational logic circuit such as a programmable logic array (hereinafter referred to as "PLA") having a programmable AND plane or OR plane, and a table look-up type logic circuit, and may have one or a plurality of flip-flop circuits (hereinafter referred to as "F/F") as necessary.
FIGS. 6 and 7 are circuit diagrams showing the conventional examples of the PLE 101. In a PLE 101 shown in FIG. 6, output signals from a programmable combinational logic circuit 103 are connected to a plurality of D input terminals of a plurality of F/Fs 104. The input signals of F/Fs 104 are subjected to a sampling by a clock signal input into a clock input terminal 105. Output terminals 106 of the D-F/Fs 104 provide output terminals of the PLE 101.
Another PLE 101' shown in FIG. 7 has substantially the same arrangement as that shown in FIG. 6. However, outputs from the programmable combinational logic circuit 103 and outputs from the D-F/F 104 are received by multiplexers 107 as their input signals and the multiplexers 107 selectively output either one of these input signals. Output terminals 108 of the multiplexers 107 are formed to provide output terminals of the PLE 101'.
However, PLDs having the above conventional construction suffer from the following problems:
(1) As shown in FIG. 6, the outputs of the PLE 101 are obtainable only from the F/Fs 104. However, it is also desirable to obtain outputs directly from the programmable combinational logic circuit 103. With the construction of FIG. 6, the only way to provide such an output is to have a PLE not having the F/F 104 for utilization. Accordingly, there occurs a case where the PLE 101 having the F/F 104 is not used or not usable.
(2) As shown in FIG. 7, multiplexer 107 can select either one of the aforesaid two outputs. Thus, the problem of the aforesaid Item (1) can be solved. However, the F/F 104 can be used only alternatively, namely to use or not to use. Accordingly, when the F/F 104s are not used, waste and inefficiency results. This waste becomes remarkable as the number of the F/Fs 104 in the PLE 101' is increased.
FIG. 8 is a conventional circuit arrangement diagram of the PLD, in which the PLE 101' has a plurality of (two in the drawing) F/Fs 104A and 104B as shown in FIG. 7. This conventional PLD has a plurality of PLEs 101' and programmable wiring 102 disposed in every vertical and horizontal directions. Similarly to that shown in FIG. 7, the PLE 101' comprises:
the programmable combinational logic circuit 103;
F/Fs 104A and 104B which receive outputs from programmable combinational circuit 103 as their inputs; and
multiplexers 107A and 107B which selectively output to the output terminals 108 either one of an output signal from respective F/Fs 104A and 104B, and an output signal from the programmable combinational logic circuit 103.
Furthermore, the programmable wirings 102 have;
switch arrays 112 capable of freely connecting respective wirings with each other at points where wirings in vertical and horizontal directions intersect each other; and
input/output switch arrays 113 capable of freely connecting the input terminals 110 and the output terminals 108 of the PLEs 101' to the respective wirings.
FIG. 9 is a connection diagram when a four bit counter circuit is formed by the conventional PLD as shown in FIG. 8. Respective output signals from the F/Fs 104A and 104B of the conventional PLE 101' together with output signals from the programmable combinational logic circuit 103 are passed through the multiplexers 107A and 107B and connected to the output terminals 108 of the PLE 101'. Accordingly, an output signal from one of the F/Fs (104A) is usually input into another PLE 101' and; when it is desired to input the aforesaid output signal into the other one of the F/Fs (104B) of the same PLE 101', it is necessary to connect through the programmable wirings 102. For this reason, four F/Fs were conventionally connected together to form a four bit counter circuit as shown in FIG. 3, as indicated by solid lines in FIG. 9. The desired connection could be achieved by programming the respective switch arrays 112, the input/output arrays 113, the programmable combinational logic circuits 103 and the multiplexers 107A and 107B. Thus, the output terminals 108 of the PLE 101' were repeatedly connected to the input terminals 110 of the original or another PLE 101', that is, to the input terminals of the programmable combinational circuits 103 of the respective PLEs 101'.
However, in the conventional PLD, when an output signal of a F/F of a PLE is connected to a F/F of the same or another PLE to form a counter circuit or the like, the output signal of the F/F is needed to be connected via programmable wirings 102 and the programmable combinational logic circuit 103, which have a relatively long delay time. Accordingly, the operatable frequency is delayed in the conventional PLE employing this arrangement.